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[Other resource] vhdl-2

Description: UART 的VHDL源代码。可在ISE, Max-Plus II,等开发环境下实现。-UART VHDL source code. The ISE, Max-Plus II, and other development environments under.
Platform: | Size: 59976 | Author: lileiming | Hits:

[VHDL-FPGA-Verilog] VHDL语言的UART串行接口芯片程序

Description: VHDL语言的UART串行接口芯片程序
Platform: | Size: 17118 | Author: redskier | Hits:

[VHDL-FPGA-Verilog] 标准的串口通讯设计VHDL

Description: 标准的异步串口通讯设计程序——基于VHDL编程-communication design programme of standard asynchronous serial port base on VHDL programme
Platform: | Size: 10240 | Author: 于飞 | Hits:

[VHDL-FPGA-Verilog] conv_code

Description: 用VHDL实现卷积码编码，该码为（2.1.3）型卷积码。-using VHDL Convolutional coding, the code (2.1.3)- Convolutional Codes.
Platform: | Size: 1024 | Author: 武汉 | Hits:

[VHDL-FPGA-Verilog] VHDL_processor

Description: 利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.-use VHDL description of a simple microprocessor, can modify the source codes to adjust instruction set, Quartus II can be directly compiled and running.
Platform: | Size: 742400 | Author: 赵康 | Hits:

[Com Port] uart_VHDL

Description: uart的vhdl实现代码 分模块设计和状态机设计 不错的，用它没错-UART achieve the VHDL code modular design and state machine design good, the right to use it
Platform: | Size: 10240 | Author: 王平 | Hits:

[Windows Develop] edaeda

Description: 完整的串行通信电路vhdl代码，已经通过quartus4.0编译-complete serial communication circuit VHDL code, the compiler has passed quartus4.0
Platform: | Size: 1024 | Author: 鲁东旭 | Hits:

[VHDL-FPGA-Verilog] ISE_uart

Description: 自己在ISE下用VHDL写的UART，简单，易懂-in ISE using VHDL was the UART, simple, understandable
Platform: | Size: 936960 | Author: sk | Hits:

[VHDL-FPGA-Verilog] vhdl-2

Description:
Platform: | Size: 59392 | Author: lileiming | Hits:

[VHDL-FPGA-Verilog] Altera_uart_VHDL

Description: FPGA/CPLD应用,uart通讯VHDL原码.-FPGA/CPLD applications, UART communications VHDL source.
Platform: | Size: 10240 | Author: cyberworm | Hits:

[VHDL-FPGA-Verilog] uartvhdl

Description: 一个在FPGA芯片上实现UART功能的vhdl源代码，提供了UART的集成-an FPGA chip to achieve UART function vhdl source code, providing integrated UART
Platform: | Size: 10240 | Author: 王利 | Hits:

[VHDL-FPGA-Verilog] uart0vhdl

Description: vhdl实现fpga和PC机的简单通信(发送),-vhdl achieve fpga and PC simple communication (transmission),
Platform: | Size: 1024 | Author: 刘音 | Hits:

[VHDL-FPGA-Verilog] uart_vhdl_lattice

Description: UART的rs232通信接口VHDL语言，里面有详细的介绍-UART communication interface rs232 VHDL language, which is described in detail
Platform: | Size: 108544 | Author: 拉拉 | Hits:

[VHDL-FPGA-Verilog] VHDL_UART

Description: VHDL语言的UART串行接口芯片程序,仅供学习使用-VHDL UART serial interface chip procedure is for learning
Platform: | Size: 4096 | Author: MINGER | Hits:

[VHDL-FPGA-Verilog] uart_core_vhdlORverilog

Description: 串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\uart 源码 (Verilog)\uart 源码 (VHDL)\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) \ uart source (Verilog) \ uart source (VHDL) \ uart16550.tar
Platform: | Size: 294912 | Author: efly | Hits:

[VHDL-FPGA-Verilog] uart-VHDL

Description: uart-VHDL 带奇偶校验位 比特率为1152-uart-VHDL add parity check bit rate is 115200
Platform: | Size: 5120 | Author: | Hits:

[VHDL-FPGA-Verilog] UART

Description: uart通用异步收发器，包括收发模块和。数据产生模块-uart transmit and reciver
Platform: | Size: 986112 | Author: 涂强 | Hits:

[VHDL-FPGA-Verilog] UART-VHDL-QUARTUS

Description: uart vhdl quartus for altera
Platform: | Size: 212992 | Author: gilang | Hits:

[VHDL-FPGA-Verilog] UART

Description: 自己总结的UART的设计及分析，已在实际工程中应用到，并且带有源代码和仿真代码，总结的文档，非常有用。(My summary of the design and analysis of UART, has been applied in practical engineering, and with source code and simulation code, summary of the document, very useful.)
Platform: | Size: 232448 | Author: 何河 | Hits:

[VHDL-FPGA-Verilog] 基于VHDL的UART控制器设计

Description: UART模块的VHDL语言设计(Design of VHDL language based on UART module)
Platform: | Size: 1039360 | Author: 周杰---123 | Hits:
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